`timescale 1ns / 1ps
module awg ( 
	input clk,
	input 				rst_n	,
	input 				CS_N		,
	input 				f_sck			,
	input 				f_mosi		,
	//output 			[3:0]led	,
	output [9:0] dac_data,
	output dac_sclk
	);
	wire clkdiv;
	wire [7:0] wave;
	wire [23:0] freq;
	wire [7:0] ampl;
	wire [3:0] led;
	assign dac_sclk=~clk;
	f_spi U1(
		.clk(clk),
		.rst_n(rst_n),
		.CS_N(CS_N),
		.SCK(f_sck),
		.MOSI(f_mosi),
		.clkdiv(clkdiv),
		.led(led),
		.wave(wave),
		.freq(freq),
		.ampl(ampl)
	);
	
	
	
	clkdiv_1M U2(
        .clk(clk),
        .rst(rst_n),
        .clkdiv(clkdiv)
    );
	
	DDS U3(
		.clk(clk)			,
		.rst_n(rst_n)		,
		.f_word	(freq)	,
		.wave_c(wave)	,
		.p_word	(10'd0)	,
		.amplitude(ampl)	,
		.dac_data(dac_data)
	);
	

 /* Port declarations.  Followed by wire,
  * reg, integer, task and function declarations
  */

 /* Describe hardware with one or more continuous 
  * assignments, always blocks, module instantiations 
  * and gate instantiations
  */



endmodule